SN54LS191 具有加/减模式控制的同步加/减计数器
The '190, 'LS190, '191, and 'LS191 are synchronous, reversible up/down counters having a complexity of 58 equivalent gates. The '191 and 'LS191 are 4-bit binary counters and the '190 and 'LS190 are BCD counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered on a low-to-high transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high
| SN54LS191 | |
| Rating | Military |
| Technology Family | LS |
SN54LS191 特性
- Counts 8-4-2-1 BCD or Binary
- Single Down/Up Count Control Line
- Count Enable Control Input
- Ripple Clock Output for Cascading
- Asynchronously Presettable with Load Control
- Parallel Outputs
- Cascadable for n-Bit Applications
SN54LS191 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LS191J | ACTIVE | -55 to 125 | 1.91 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS191FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LS191J | ACTIVE | -55 to 125 | 3.46 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS191W | ACTIVE | -55 to 125 | 15.12 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54LS191 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LS191J | TBD | A42 | N/A for Pkg Type | SN54LS191J | SN54LS191J |
| SNJ54LS191FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS191FK | SNJ54LS191FK |
| SNJ54LS191J | TBD | A42 | N/A for Pkg Type | SNJ54LS191J | SNJ54LS191J |
| SNJ54LS191W | TBD | A42 | N/A for Pkg Type | SNJ54LS191W | SNJ54LS191W |
SN54LS191 应用技术支持与电子电路设计开发资源下载
- SN54LS191 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)