SN54LS165A-SP 并联负载 8 位移位寄存器
The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD\) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD\ high enables the other clock input
| SN54LS165A-SP | |
| Technology Family | LS |
| Rating | Space |
SN54LS165A-SP 特性
- Complementary Outputs
- Direct Overriding Load (Data) Inputs
- Gated Clock Inputs
- Parallel-to-Serial Data Conversion
SN54LS165A-SP 应用技术支持与电子电路设计开发资源下载
- SN54LS165A-SP 数据资料 dataSheet 下载.PDF
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