These 8-bit shift registers feature gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup-time requirements will be entered. Clocking occurs on the low-to-high-level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.
The SN54164 and SN54LS164 are characterized for operation over the full military temperature range of -55°C to 125°
SN54LS164 | |
Technology Family | LS |
Rating | Military |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN54LS164J | ACTIVE | -55 to 125 | 16.23 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
SNJ54LS164FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
SNJ54LS164J | ACTIVE | -55 to 125 | 23.81 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
SNJ54LS164W | ACTIVE | -55 to 125 | 16.23 | 1ku | CFP (W) | 14 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN54LS164J | TBD | A42 | N/A for Pkg Type | SN54LS164J | SN54LS164J |
SNJ54LS164FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS164FK | SNJ54LS164FK |
SNJ54LS164J | TBD | A42 | N/A for Pkg Type | SNJ54LS164J | SNJ54LS164J |
SNJ54LS164W | TBD | Call TI | N/A for Pkg Type | SNJ54LS164W | SNJ54LS164W |