These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic ensures that all inputs remain off for all invalid input conditions.
SN54HC42 | |
Rating | Military |
Technology Family | HC |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SNJ54HC42FK | ACTIVE | -55 to 125 | 11.77 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
SNJ54HC42J | ACTIVE | -55 to 125 | 2.49 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
SNJ54HC42W | ACTIVE | -55 to 125 | 12.36 | 1ku | CFP (W) | 16 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SNJ54HC42FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54HC42FK | SNJ54HC42FK |
SNJ54HC42J | TBD | A42 | N/A for Pkg Type | SNJ54HC42J | SNJ54HC42J |
SNJ54HC42W | TBD | A42 | N/A for Pkg Type | SNJ54HC42W | SNJ54HC42W |