Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections.
The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives the bus line to a high or low logic level. Each output has its own output-enable (OE)\ input. The outputs are disabled when their respective OE\ is high
SN54HC253 | |
Rating | Military |
Technology Family | HC |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN54HC253J | ACTIVE | -55 to 125 | 15.25 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
SNJ54HC253J | ACTIVE | -55 to 125 | 12.46 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
SNJ54HC253W | ACTIVE | -55 to 125 | 18.57 | 1ku | CFP (W) | 16 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN54HC253J | TBD | Call TI | N/A for Pkg Type | SN54HC253J | SN54HC253J |
SNJ54HC253J | TBD | Call TI | N/A for Pkg Type | SNJ54HC253J | SNJ54HC253J |
SNJ54HC253W | TBD | A42 | N/A for Pkg Type | SNJ54HC253W | SNJ54HC253W |