SN54HC195 4 位并行访问移位寄存器

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table

	SN54HC195
Technology Family	HC
Rating	Military

SN54HC195 特性

• Synchronous Parallel Load
• Positive-Edge-Triggered Clocking
• J and K Inputs to First Stage
• Complementary Outputs From Last Stage
• Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers
• Dependable Texas lnstruments Quality and Reliability

SN54HC195 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN54HC195J	ACTIVE	-55 to 125	16.23 | 1ku	CDIP (J) | 16	1 | TUBE
SNJ54HC195FK	ACTIVE	-55 to 125	17.37 | 1ku	LCCC (FK) | 20	1 | TUBE
SNJ54HC195J	ACTIVE	-55 to 125	23.81 | 1ku	CDIP (J) | 16	1 | TUBE
SNJ54HC195W	ACTIVE	-55 to 125	16.23 | 1ku	CFP (W) | 16	1 | TUBE

SN54HC195 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54HC195J	TBD	A42	N/A for Pkg Type	SN54HC195J	SN54HC195J
SNJ54HC195FK	TBD	POST-PLATE	N/A for Pkg Type	SNJ54HC195FK	SNJ54HC195FK
SNJ54HC195J	TBD	A42	N/A for Pkg Type	SNJ54HC195J	SNJ54HC195J
SNJ54HC195W	TBD	Call TI	N/A for Pkg Type	SNJ54HC195W	SNJ54HC195W

SN54HC195 应用技术支持与电子电路设计开发资源下载

1. SN54HC195 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)