The ’HC191 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a low- to high-level transition of the clock (CLK) input if the count-enable (CTEN)\ input is low. A high at CTEN\ inhibits counting. The direction of the count is determined by the level of the down/up (D/U\) input. When D/U\ is low, the counter counts up, and when D/U\ is high, it counts down
SN54HC191 | |
Rating | Military |
Technology Family | HC |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN54HC191J | ACTIVE | -55 to 125 | 1.91 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
SNJ54HC191FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
SNJ54HC191J | ACTIVE | -55 to 125 | 3.46 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
SNJ54HC191W | ACTIVE | -55 to 125 | 15.12 | 1ku | CFP (W) | 16 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN54HC191J | TBD | A42 | N/A for Pkg Type | SN54HC191J | SN54HC191J |
SNJ54HC191FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54HC191FK | SNJ54HC191FK |
SNJ54HC191J | TBD | A42 | N/A for Pkg Type | SNJ54HC191J | SNJ54HC191J |
SNJ54HC191W | TBD | A42 | N/A for Pkg Type | SNJ54HC191W | SNJ54HC191W |