SN54HC139 双路 2 线路至 4 线路解码器/多路解复用器

The ’HC139 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The ’HC139 devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G\) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit

	SN54HC139
Rating	Military
Technology Family	HC

SN54HC139 特性

• Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
• Wide Operating Voltage Range of 2 V to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80-uA Max ICC
• Typical tpd = 10 ns
• ±4-mA Output Drive at 5 V
• Low Input Current of 1 uA Max
• Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception

SN54HC139 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SNJ54HC139FK	ACTIVE	-55 to 125	11.77 | 1ku	LCCC (FK) | 20	1 | TUBE
SNJ54HC139J	ACTIVE	-55 to 125	2.49 | 1ku	CDIP (J) | 16	1 | TUBE
SNJ54HC139W	ACTIVE	-55 to 125	12.36 | 1ku	CFP (W) | 16	1 | TUBE

SN54HC139 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SNJ54HC139FK	TBD	POST-PLATE	N/A for Pkg Type	SNJ54HC139FK	SNJ54HC139FK
SNJ54HC139J	TBD	A42	N/A for Pkg Type	SNJ54HC139J	SNJ54HC139J
SNJ54HC139W	TBD	A42	N/A for Pkg Type	SNJ54HC139W	SNJ54HC139W

SN54HC139 应用技术支持与电子电路设计开发资源下载

1. SN54HC139 数据资料 dataSheet 下载.PDF
2. TI 德州仪器MSI 功能产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)