SN54GTL16612 18 位 GTL/LVT 通用总线收发器
The 'GTL16612 devices are 18-bit UBTTM transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OECTM circuitry.
The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1
|
SN54GTL16612 |
| Voltage Nodes(V) |
5, 3.3 |
| A Side |
LVTTL |
| B Side |
GTL |
| Fclock(Max)(MHz) |
|
| Bus Drive(ma) |
-32/64 |
| No. of Bits |
18 |
| th(ns) |
3.4 |
| tsu(ns) |
3.2 |
| Static Current |
5 |
| Rating |
Military |
| Technology Family |
GTL |
SN54GTL16612 特性
- Members of Texas Instruments' WidebusTM Family
- UBTTM Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes
- OECTM Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
- Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels
- Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs
- Identical to \x9216601 Function
- Ioff Supports Partial-Power-Down Mode Operation
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Latch-Up Performance Exceeds 500 mA Per JESD 17
SN54GTL16612 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 5962-9689001QXA |
ACTIVE |
-55 to 125 |
41.03 | 1ku |
CFP (WD) | 56 |
1 | TUBE |
|
| SNJ54GTL16612WD |
ACTIVE |
-55 to 125 |
41.03 | 1ku |
CFP (WD) | 56 |
1 | TUBE |
|
SN54GTL16612 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 5962-9689001QXA |
TBD |
A42 |
N/A for Pkg Type |
5962-9689001QXA |
5962-9689001QXA |
| SNJ54GTL16612WD |
TBD |
A42 |
N/A for Pkg Type |
SNJ54GTL16612WD |
SNJ54GTL16612WD |
SN54GTL16612 应用技术支持与电子电路设计开发资源下载
- SN54GTL16612 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)