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SN54BCT8244A 具有八路缓冲器的扫描测试设备

The 'BCT8244A scan test devices with octal buffers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F244 and 'BCT244 octal buffers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal buffers

SN54BCT8244A
Voltage Nodes(V) 5
Vcc range(V) 4.5 to 5.5
Input Level TTL
Logic True
No. of Outputs 8
Output Drive(mA) -15/64
tpd max(ns) 8.5
Output Level TTL
Static Current 29.75
Rating Military
Technology Family BCT
SN54BCT8244A 特性
SN54BCT8244A 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
5962-9172601M3A ACTIVE -55 to 125 36.37 | 1ku LCCC (FK) | 28 1 | TUBE  
5962-9172601MLA ACTIVE -55 to 125 23.36 | 1ku CDIP (JT) | 24 1 | TUBE  
SNJ54BCT8244AFK ACTIVE -55 to 125 36.37 | 1ku LCCC (FK) | 28 1 | TUBE  
SNJ54BCT8244AJT ACTIVE -55 to 125 23.36 | 1ku CDIP (JT) | 24 1 | TUBE  
SN54BCT8244A 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
5962-9172601M3A TBD POST-PLATE N/A for Pkg Type 5962-9172601M3A 5962-9172601M3A
5962-9172601MLA TBD A42 N/A for Pkg Type 5962-9172601MLA 5962-9172601MLA
SNJ54BCT8244AFK TBD POST-PLATE N/A for Pkg Type SNJ54BCT8244AFK SNJ54BCT8244AFK
SNJ54BCT8244AJT TBD A42 N/A for Pkg Type SNJ54BCT8244AJT SNJ54BCT8244AJT
SN54BCT8244A 应用技术支持与电子电路设计开发资源下载
  1. SN54BCT8244A 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器特殊逻辑产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)