SN54BCT373 具有三态输出的八路透明 D 类锁存器

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’BCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly

	SN54BCT373
Voltage Nodes(V)	5
Rating	Military

SN54BCT373 特性

• Operating Voltage Range of 4.5 V to 5.5 V
• State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
• Full Parallel Access for Loading
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)

SN54BCT373 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SNJ54BCT373FK	ACTIVE	5962-9074601M2A	19.16 | 1ku	LCCC (FK) | 20	1 | TUBE
SNJ54BCT373J	ACTIVE	5962-9074601MRA	12.02 | 1ku	CDIP (J) | 20	1 | TUBE
SNJ54BCT373W	ACTIVE	5962-9074601MSA	13.44 | 1ku	CFP (W) | 20	1 | TUBE

SN54BCT373 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SNJ54BCT373FK	TBD	POST-PLATE	N/A for Pkg Type	SNJ54BCT373FK	SNJ54BCT373FK
SNJ54BCT373J	TBD	A42	N/A for Pkg Type	SNJ54BCT373J	SNJ54BCT373J
SNJ54BCT373W	TBD	Call TI	N/A for Pkg Type	SNJ54BCT373W	SNJ54BCT373W

SN54BCT373 应用技术支持与电子电路设计开发资源下载

1. SN54BCT373 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)