These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (,) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters
SN54AS867 | |
Rating | Military |
Technology Family | ALS |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN54AS867JT | ACTIVE | -55 to 125 | 15.70 | 1ku | CDIP (J) | 24 | 1 | TUBE | |
SNJ54AS867FK | ACTIVE | -55 to 125 | 10.68 | 1ku | LCCC (FK) | 28 | 1 | TUBE | |
SNJ54AS867JT | ACTIVE | -55 to 125 | 18.37 | 1ku | CDIP (J) | 24 | 1 | TUBE | |
SNJ54AS867W | ACTIVE | -55 to 125 | 10.68 | 1ku | CFP (W) | 24 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN54AS867JT | TBD | A42 | N/A for Pkg Type | SN54AS867JT | SN54AS867JT |
SNJ54AS867FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54AS867FK | SNJ54AS867FK |
SNJ54AS867JT | TBD | A42 | N/A for Pkg Type | SNJ54AS867JT | SNJ54AS867JT |
SNJ54AS867W | TBD | A42 | N/A for Pkg Type | SNJ54AS867W | SNJ54AS867W |