SN54AS823A 具有三态输出的 9 位总线接口触发器
These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers.
With the clock-enable (
) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking high disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has inverting (D\) inputs. Taking the clear (
) input low causes the nine Q outputs to go low independently of the clock
SN54AS823A 特性
- Functionally Equivalent to AMD's AM29823 and AM29824
- Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
- Outputs Have Undershoot-Protection Circuitry
- Power-Up High-Impedance State
- Buffered Control Inputs to Reduce dc Loading Effects
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54AS823A 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SNJ54AS823AFK |
ACTIVE |
-55 to 125 |
9.75 | 1ku |
LCCC (FK) | 28 |
1 | TUBE |
|
| SNJ54AS823AJ |
ACTIVE |
-55 to 125 |
5.95 | 1ku |
CDIP (J) | 24 |
1 | TUBE |
|
| SNJ54AS823AWD |
ACTIVE |
-55 to 125 |
10.35 | 1ku |
CFP (W) | 24 |
1 | TUBE |
|
SN54AS823A 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SNJ54AS823AFK |
TBD |
POST-PLATE |
N/A for Pkg Type |
SNJ54AS823AFK |
SNJ54AS823AFK |
| SNJ54AS823AJ |
TBD |
A42 |
N/A for Pkg Type |
SNJ54AS823AJ |
SNJ54AS823AJ |
| SNJ54AS823AWD |
TBD |
Call TI |
N/A for Pkg Type |
SNJ54AS823AWD |
SNJ54AS823AWD |
SN54AS823A 应用技术支持与电子电路设计开发资源下载
- SN54AS823A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)