SN54AS574 具有三态输出的八路 D 类边沿触发器

These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear () input low.

The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of -55°C to 125°C

	SN54AS574
Voltage Nodes(V)	5
Rating	Military

SN54AS574 特性

• 3-State Buffer-Type Noninverting Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Buffered Control Inputs
• SN74ALS575A and 'AS575 Have Synchronous Clear
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N, NT) and Ceramic (J, JT) 300-mil DIPs, and Ceramic Flat (W) Packages

SN54AS574 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SNJ54AS574FK	ACTIVE	-55 to 125	9.75 | 1ku	LCCC (FK) | 20	1 | TUBE
SNJ54AS574J	ACTIVE	-55 to 125	5.95 | 1ku	CDIP (J) | 20	1 | TUBE
SNJ54AS574WD	ACTIVE	-55 to 125	10.35 | 1ku	CFP (W) | 20	1 | TUBE

SN54AS574 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SNJ54AS574FK	TBD	POST-PLATE	N/A for Pkg Type	SNJ54AS574FK	SNJ54AS574FK
SNJ54AS574J	TBD	A42	N/A for Pkg Type	SNJ54AS574J	SNJ54AS574J
SNJ54AS574WD	TBD	Call TI	N/A for Pkg Type	SNJ54AS574WD	SNJ54AS574WD

SN54AS574 应用技术支持与电子电路设计开发资源下载

1. SN54AS574 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)