SN54AS138 3 线路至 8 线路解码器/多路解复用器
The 'ALS138A and 'AS138 are 3-line to 8-line decoders/demultiplexers designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible.
The conditions at the binary-select (A, B, and C) inputs and the three enable (G1, 
, and 
) inputs select one of eight output lines
|
SN54AS138 |
| Rating |
Military |
| Technology Family |
AS |
SN54AS138 特性
- Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
- Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54AS138 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SNJ54AS138FK |
ACTIVE |
-55 to 125 |
11.77 | 1ku |
LCCC (FK) | 20 |
1 | TUBE |
|
| SNJ54AS138J |
ACTIVE |
-55 to 125 |
2.49 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
| SNJ54AS138W |
ACTIVE |
-55 to 125 |
12.36 | 1ku |
CFP (W) | 16 |
1 | TUBE |
|
SN54AS138 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SNJ54AS138FK |
TBD |
POST-PLATE |
N/A for Pkg Type |
SNJ54AS138FK |
SNJ54AS138FK |
| SNJ54AS138J |
TBD |
A42 |
N/A for Pkg Type |
SNJ54AS138J |
SNJ54AS138J |
| SNJ54AS138W |
TBD |
A42 |
N/A for Pkg Type |
SNJ54AS138W |
SNJ54AS138W |
SN54AS138 应用技术支持与电子电路设计开发资源下载
- SN54AS138 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)