SN54ALS874B 具有三态输出的八路 4 位 D 类边沿触发器

These dual 4-bit D-type edge-triggered flip-flops feature 3-state outputs designed specifically as bus drivers. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The edge-triggered flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN54ALS874B, SN74ALS874B, and SN74AS874 have clear () inputs and noninverting Q outputs. The SN74ALS876A and SN74AS876 have preset () inputs and inverting Q\ outputs; taking low causes the four Q or Q\ outputs to go low independently of the clock.

The SN54ALS874B is characterized for operation over the full military temperature range of -55°C to 125°C

	SN54ALS874B
Voltage Nodes(V)	5
Rating	Military

SN54ALS874B 特性

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Choice of True or Inverting Logic
  • SN54ALS874B, SN74ALS874B, SN74AS874 Have True Outputs
  • SN74ALS876A, SN74AS876 Have Inverting Outputs
• Asynchronous Clear
• Package Options Include Plastic Small-Outline (DW) Packages, Plastic (FN) and Ceramic (FK) Chip Carriers, and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

SN54ALS874B 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SNJ54ALS874BFK	ACTIVE	-55 to 125	9.75 | 1ku	LCCC (FK) | 24	1 | TUBE
SNJ54ALS874BJ	ACTIVE	-55 to 125	5.95 | 1ku	CDIP (J) | 28	1 | TUBE
SNJ54ALS874BWD	ACTIVE	-55 to 125	10.35 | 1ku	CFP (W) | 24	1 | TUBE

SN54ALS874B 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SNJ54ALS874BFK	TBD	POST-PLATE	N/A for Pkg Type	SNJ54ALS874BFK	SNJ54ALS874BFK
SNJ54ALS874BJ	TBD	A42	N/A for Pkg Type	SNJ54ALS874BJ	SNJ54ALS874BJ
SNJ54ALS874BWD	TBD	Call TI	N/A for Pkg Type	SNJ54ALS874BWD	SNJ54ALS874BWD

SN54ALS874B 应用技术支持与电子电路设计开发资源下载

1. SN54ALS874B 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)