SN54ALS137A 具有地址锁存器的 3 线路到 8 线路解码器/多路解复用器
The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/demultiplexers with latches on the three address inputs. When the latch-enable (
) input is low, the devices act as decoders/demultiplexers. When goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as remains high. The output-enable controls (G1 and G2\) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2\ is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.
The SN54ALS137A is characterized for operation over the full military temperature range of -55°C to 125°C
SN54ALS137A 特性
- Combines Decoder and 3-Bit Address Latch
- Incorporates Two Output Enables to Simplify Cascading
- Package Options Include Plastic Small- Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54ALS137A 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SNJ54ALS137AFK |
ACTIVE |
-55 to 125 |
11.77 | 1ku |
LCCC (FK) | 20 |
1 | TUBE |
|
| SNJ54ALS137AJ |
ACTIVE |
-55 to 125 |
2.49 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
| SNJ54ALS137AW |
ACTIVE |
-55 to 125 |
12.36 | 1ku |
CFP (W) | 16 |
1 | TUBE |
|
SN54ALS137A 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SNJ54ALS137AFK |
TBD |
POST-PLATE |
N/A for Pkg Type |
SNJ54ALS137AFK |
SNJ54ALS137AFK |
| SNJ54ALS137AJ |
TBD |
A42 |
N/A for Pkg Type |
SNJ54ALS137AJ |
SNJ54ALS137AJ |
| SNJ54ALS137AW |
TBD |
A42 |
N/A for Pkg Type |
SNJ54ALS137AW |
SNJ54ALS137AW |
SN54ALS137A 应用技术支持与电子电路设计开发资源下载
- SN54ALS137A 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)