SN54AHCT138 3 线路到 8 线路解码器/多路解复用器

The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding

	SN54AHCT138
Rating	Military
Technology Family	AHCT

SN54AHCT138 特性

• Inputs Are TTL-Voltage Compatible
• Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
• Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

SN54AHCT138 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SNJ54AHCT138FK	ACTIVE	-55 to 125	11.77 | 1ku	LCCC (FK) | 20	1 | TUBE
SNJ54AHCT138J	ACTIVE	-55 to 125	2.49 | 1ku	CDIP (J) | 16	1 | TUBE
SNJ54AHCT138W	ACTIVE	-55 to 125	12.36 | 1ku	CFP (W) | 16	1 | TUBE

SN54AHCT138 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SNJ54AHCT138FK	TBD	POST-PLATE	N/A for Pkg Type	SNJ54AHCT138FK	SNJ54AHCT138FK
SNJ54AHCT138J	TBD	A42	N/A for Pkg Type	SNJ54AHCT138J	SNJ54AHCT138J
SNJ54AHCT138W	TBD	A42	N/A for Pkg Type	SNJ54AHCT138W	SNJ54AHCT138W

SN54AHCT138 应用技术支持与电子电路设计开发资源下载

1. SN54AHCT138 数据资料 dataSheet 下载.PDF
2. TI 德州仪器MSI 功能产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)