These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR)\ input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output
SN54AHC273 | |
Voltage Nodes(V) | 5 |
Rating | Military |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN54AHC273J | ACTIVE | -55 to 125 | 4.24 | 1ku | CDIP (J) | 20 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN54AHC273J | TBD | A42 | N/A for Pkg Type | SN54AHC273J | SN54AHC273J |