The SN54ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 15 ns. The 1024 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.
| SN54ACT3641 | |
| Depth | 1024 |
| Width | 36 |
| Fmax(MHz) | 50 |
| Sync/Async | S |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Technology Family | ACT |
| Rating | Military |
| 器件 | 状态 | 温度 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54ACT3641HFP | PREVIEW | -55 to 125 | CFP (HFP) | 132 | 1 | JEDEC TRAY (5+1) |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54ACT3641HFP | TBD | POST-PLATE | N/A for Pkg Type | SNJ54ACT3641HFP | SNJ54ACT3641HFP |