SN54ACT3632 512 x 18 x 2 同步双向 FIFO 存储器

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths.

The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface

	SN54ACT3632
Depth	512
Width	36
Fmax(MHz)	50
Sync/Async	S
Voltage Nodes(V)	5
Vcc range(V)	4.5 to 5.5
Technology Family	ACT
Rating	Military

SN54ACT3632 特性

• Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
• Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions
• Mailbox-Bypass Register for Each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor Interface Control Logic
• IRA, ORA, AEA\, and AFA\ Flags Synchronized by CLKA
• Released as DESC SMD (Standard Microcircuit Drawing) 5962-9562801QYA
• IRB, ORB, AEB\, and AFB\ Flags Synchronized by CLKB
• Low-Power 0.8-um Advanced CMOS Technology
• Supports Clock Frequencies up to 50 MHz
• Fast Access Times of 13 ns
• Packaged in 132-Pin Ceramic Quad Flat Package

SN54ACT3632 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN54ACT3632HFP	ACTIVE	-55 to 125	225.01 | 1ku	CFP (HFP) | 132	1 | JEDEC TRAY (5+1)

SN54ACT3632 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54ACT3632HFP	TBD	POST-PLATE	N/A for Pkg Type	SN54ACT3632HFP	SN54ACT3632HFP

SN54ACT3632 应用技术支持与电子电路设计开发资源下载

1. SN54ACT3632 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)