The ’AC74 devices are dual positive-edge-triggered D-type flip-flops.
A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs
| SN54AC74-SP | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output | 2S |
| No. of Bits | 1 |
| Technology Family | TTL |
| Rating | Military |
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54AC74-SPJ | ACTIVE | -55 to 125 | 4.24 | 1ku | CDIP (J) | 20 | 1 | TUBE |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54AC74-SPJ | TBD | A42 | N/A for Pkg Type | SN54AC74-SPJ | SN54AC74-SPJ |