A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN54ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It processes data at rates up to 40 MHz, with access times of 18 ns in a bit-parallel format.
The SN54ABT7820 consists of bus transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs GAB and GBA control the transceiver functions. The SAB and SBA control inputs select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data
| SN54ABT7820 | SN74ABT7820 | |
| Depth | 512 | 512 |
| Width | 18 | 18 |
| Fmax(MHz) | 40 | 67 |
| Sync/Async | A | A |
| Voltage Nodes(V) | 5 | 5 |
| Vcc range(V) | 4.5 to 5.5 | 4.5 to 5.5 |
| Output Drive(mA) | -12/24 | |
| Rating | Military | Catalog |
| Technology Family | ABT | ABT |
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 5962-9650901QXA | ACTIVE | -55 to 125 | 120.18 | 1ku | CPGA (GB) | 84 | 1 | JEDEC TRAY (5+1) | |
| SNJ54ABT7820GB | ACTIVE | -55 to 125 | 120.18 | 1ku | CPGA (GB) | 84 | 1 | JEDEC TRAY (5+1) |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 5962-9650901QXA | TBD | POST-PLATE | N/A for Pkg Type | 5962-9650901QXA | 5962-9650901QXA |
| SNJ54ABT7820GB | TBD | POST-PLATE | N/A for Pkg Type | SNJ54ABT7820GB | SNJ54ABT7820GB |