A FIFO memory is a storage device that allows data to be read from its array in the same order it is written. The SN54ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. Two independent 512 × 18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.
The SN54ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident
| SN54ABT7819 | |
| Depth | 512 |
| Width | 18 |
| Fmax(MHz) | 50 |
| Sync/Async | S |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Technology Family | ABT |
| Rating | Military |
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 5962-9470401QXA | ACTIVE | -55 to 125 | 284.63 | 1ku | CPGA (GB) | 84 | 1 | JEDEC TRAY (5+1) | |
| SNJ54ABT7819GB | ACTIVE | -55 to 125 | 284.63 | 1ku | CPGA (GB) | 84 | 1 | JEDEC TRAY (5+1) |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 5962-9470401QXA | TBD | POST-PLATE | N/A for Pkg Type | 5962-9470401QXA | 5962-9470401QXA |
| SNJ54ABT7819GB | TBD | POST-PLATE | N/A for Pkg Type | SNJ54ABT7819GB | SNJ54ABT7819GB |