SN54ABT377 具有时钟使能输入的八路边沿 D 类触发器

These 8-bit positive-edge-triggered D-type flip-flops with a clock (CLK) input are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Data (D) input information that meets the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the common clock-enable ( input is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the buffered clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at

	SN54ABT377
Voltage Nodes(V)	5
Vcc range(V)	4.5 to 5.5
Input Level	TTL
Output Level	TTL
Output	2S
No. of Bits	1
Technology Family	TTL
Rating	Military

SN54ABT377 特性

• State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
• High-Drive Outputs (-32-mA IOH, 64-mA IOL)
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

SN54ABT377 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN54ABT377J	ACTIVE	-55 to 125	4.24 | 1ku	CDIP (J) | 14	1 | TUBE

SN54ABT377 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54ABT377J	TBD	A42	N/A for Pkg Type	SN54ABT377J	SN54ABT377J

SN54ABT377 应用技术支持与电子电路设计开发资源下载

1. SN54ABT377 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)