SN54ABT16823 具有三态输出的 18 位总线接口触发器

These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable () input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking high disables the clock buffer, latching the outputs. Taking the clear () input low causes the Q outputs to go low independently of the clock.

A buffered output-enable () input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state

	SN54ABT16823
Voltage Nodes(V)	5
Technology Family	ABT
Rating	Military

SN54ABT16823 特性

• Members of the Texas Instruments WidebusTM Family
• State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
• High-Impedance State During Power Up and Power Down
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
• Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• High-Drive Outputs (-32-mA IOH, 64-mA IOL)
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

SN54ABT16823 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SNJ54ABT16823WD	ACTIVE	-55 to 125	40.25 | 1ku	CFP (WD) | 56	1 | TUBE

SN54ABT16823 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SNJ54ABT16823WD	TBD	A42	N/A for Pkg Type	SNJ54ABT16823WD	SNJ54ABT16823WD

SN54ABT16823 应用技术支持与电子电路设计开发资源下载

1. SN54ABT16823 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)