SN54ABT16601 具有三态输出的 18 位通用总线收发器
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (
and 
), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (
and 
) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable is active low. When is low, the outputs are active
|
SN54ABT16601 |
| Voltage Nodes(V) |
5 |
| Vcc range(V) |
4.5 to 5.5 |
| Input Level |
TTL |
| Output Level |
TTL |
| No. of Outputs |
18 |
| Logic |
True |
| Rating |
Military |
| Technology Family |
ABT |
SN54ABT16601 特性
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
- Flow-Through Architecture Optimizes PCB Layout
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16601 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 5962-9467101QXA |
ACTIVE |
-55 to 125 |
25.62 | 1ku |
CFP (WD) | 56 |
1 | TUBE |
|
| SNJ54ABT16601WD |
ACTIVE |
-55 to 125 |
25.62 | 1ku |
CFP (WD) | 56 |
1 | TUBE |
|
SN54ABT16601 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 5962-9467101QXA |
TBD |
A42 |
N/A for Pkg Type |
5962-9467101QXA |
5962-9467101QXA |
| SNJ54ABT16601WD |
TBD |
A42 |
N/A for Pkg Type |
SNJ54ABT16601WD |
SNJ54ABT16601WD |
SN54ABT16601 应用技术支持与电子电路设计开发资源下载
- SN54ABT16601 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)