The '76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The '76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS76A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table
SN5476 | |
Voltage Nodes(V) | 5 |
Vcc range(V) | 4.5 to 5.5 |
Input Level | TTL |
Output Level | TTL |
Output | 2S |
No. of Bits | 1 |
Technology Family | TTL |
Rating | Military |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN5476J | ACTIVE | -55 to 125 | 4.24 | 1ku | CDIP (J) | 14 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN5476J | TBD | A42 | N/A for Pkg Type | SN5476J | SN5476J |