These J-K flip-flops are based on the master-slave principle and each has AND gate inputs for entry into the master section which are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
The logical states of the J and K inputs must not be allowed to change when the clock pulse is in a high state.
The SN5472, and the SN54H72 are characterized for operation over the full military temperature range of -55°C to 125°C
SN5472 | |
Voltage Nodes(V) | 5 |
Vcc range(V) | 4.5 to 5.5 |
Input Level | TTL |
Output Level | TTL |
Output | 2S |
No. of Bits | 1 |
Technology Family | TTL |
Rating | Military |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN5472J | ACTIVE | -55 to 125 | 4.24 | 1ku | CDIP (J) | 14 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN5472J | TBD | A42 | N/A for Pkg Type | SN5472J | SN5472J |