CY74FCT841CT 具有三态输出的八路透明 D 类锁存器
The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.
The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
| CY74FCT841CT | |
| Voltage Nodes(V) | 5 |
| Rating | Catalog |
CY74FCT841CT 特性
- Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Fully Compatible With TTL Input and Output Logic Levels
- High-Speed Parallel Latches
- Buffered Common Latch-Enable Input
- 3-State Outputs
- CY54FCT841T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT841T
- 64-mA Output Sink Current
- 32-mA Output Source Current
CY74FCT841CT 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| CY74FCT841CTSOC | ACTIVE | -40 to 85 | 0.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| CY74FCT841CTSOCE4 | ACTIVE | -40 to 85 | 0.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| CY74FCT841CTSOCG4 | ACTIVE | -40 to 85 | 0.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| CY74FCT841CTSOCT | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 2000 | LARGE T&R | |
| CY74FCT841CTSOCTE4 | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 2000 | LARGE T&R | |
| CY74FCT841CTSOCTG4 | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 2000 | LARGE T&R |
CY74FCT841CT 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| CY74FCT841CTSOC | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CY74FCT841CTSOC | CY74FCT841CTSOC |
| CY74FCT841CTSOCE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CY74FCT841CTSOCE4 | CY74FCT841CTSOCE4 |
| CY74FCT841CTSOCG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CY74FCT841CTSOCG4 | CY74FCT841CTSOCG4 |
| CY74FCT841CTSOCT | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CY74FCT841CTSOCT | CY74FCT841CTSOCT |
| CY74FCT841CTSOCTE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CY74FCT841CTSOCTE4 | CY74FCT841CTSOCTE4 |
| CY74FCT841CTSOCTG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CY74FCT841CTSOCTG4 | CY74FCT841CTSOCTG4 |
CY74FCT841CT 应用技术支持与电子电路设计开发资源下载
- CY74FCT841CT 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)