CY74FCT162H501CT 具有总线保留和三态输出的 18 位通用总线收发器
These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA\), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOWlogic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA\, LEBA, and CLKBA.
This device is fully specified for partial-power-down applications using Ioff
CY74FCT162H501CT 特性
- Ioff supports partial-power-down mode operation
- Edge-rate control circuitry for significantly improved noise characteristics
- Typical output skew < 250 ps
- ESD > 2000V
- TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages
- Industrial temperature range of -40°C to +85°C
- VCC = 5V ± 10%
- CY74FCT16501T Features:
- 64 mA sink current, 32 mA source current
- Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25°C
- CY74FCT162501T Features:
- Balanced 24 mA output drivers
- Reduced system switching noise
- Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA = 25°C
- CY74FCT162H501T Features:
- Bus hold retains last active state
- Eliminates the need for external pull-up or pull-down resistors
CY74FCT162H501CT 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 74FCT162H501CTPACT |
ACTIVE |
-40 to 85 |
1.40 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| 74FCT162H501CTPVCT |
ACTIVE |
-40 to 85 |
1.50 | 1ku |
SSOP (DL) | 56 |
1000 | LARGE T&R |
|
| FCT162H501CTPACTE4 |
ACTIVE |
-40 to 85 |
1.40 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| FCT162H501CTPACTG4 |
ACTIVE |
-40 to 85 |
1.40 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| FCT162H501CTPVCTG4 |
ACTIVE |
-40 to 85 |
1.50 | 1ku |
SSOP (DL) | 56 |
1000 | LARGE T&R |
|
CY74FCT162H501CT 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 74FCT162H501CTPACT |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74FCT162H501CTPACT |
74FCT162H501CTPACT |
| 74FCT162H501CTPVCT |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74FCT162H501CTPVCT |
74FCT162H501CTPVCT |
| FCT162H501CTPACTE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
FCT162H501CTPACTE4 |
FCT162H501CTPACTE4 |
| FCT162H501CTPACTG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
FCT162H501CTPACTG4 |
FCT162H501CTPACTG4 |
| FCT162H501CTPVCTG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
FCT162H501CTPVCTG4 |
FCT162H501CTPVCTG4 |
CY74FCT162H501CT 应用技术支持与电子电路设计开发资源下载
- CY74FCT162H501CT 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)