CY54FCT273T 具有清零端的八路 D 类触发器
The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
CY54FCT273T 特性
- Function, Pinout, and Drive Compatible With FCT and F Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Fully Compatible With TTL Input and Output Logic Levels
- CY54FCT273T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT273T
- 64-mA Output Sink Current
- 32-mA Output Source Current
CY54FCT273T 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CY54FCT273TE |
ACTIVE |
-55 to 125 |
0.55 | 1ku |
PDIP (N) | 20 |
25 | TUBE |
|
| CY54FCT273TEE4 |
ACTIVE |
-55 to 125 |
0.55 | 1ku |
PDIP (N) | 20 |
25 | TUBE |
|
| CY54FCT273TM |
ACTIVE |
-55 to 125 |
0.48 | 1ku |
SOIC (DW) | 20 |
40 | TUBE |
|
| CY54FCT273TM96 |
ACTIVE |
-55 to 125 |
0.40 | 1ku |
SOIC (DW) | 20 |
2500 | LARGE T&R |
|
| CY54FCT273TM96E4 |
ACTIVE |
-55 to 125 |
0.40 | 1ku |
SOIC (DW) | 20 |
2500 | LARGE T&R |
|
| CY54FCT273TM96G4 |
ACTIVE |
-55 to 125 |
0.40 | 1ku |
SOIC (DW) | 20 |
2500 | LARGE T&R |
|
| CY54FCT273TME4 |
ACTIVE |
-55 to 125 |
0.48 | 1ku |
SOIC (DW) | 20 |
40 | TUBE |
|
| CY54FCT273TMG4 |
ACTIVE |
-55 to 125 |
0.48 | 1ku |
SOIC (DW) | 20 |
40 | TUBE |
|
CY54FCT273T 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CY54FCT273TE |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CY54FCT273TE |
CY54FCT273TE |
| CY54FCT273TEE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CY54FCT273TEE4 |
CY54FCT273TEE4 |
| CY54FCT273TM |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CY54FCT273TM |
CY54FCT273TM |
| CY54FCT273TM96 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CY54FCT273TM96 |
CY54FCT273TM96 |
| CY54FCT273TM96E4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CY54FCT273TM96E4 |
CY54FCT273TM96E4 |
| CY54FCT273TM96G4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CY54FCT273TM96G4 |
CY54FCT273TM96G4 |
| CY54FCT273TME4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CY54FCT273TME4 |
CY54FCT273TME4 |
| CY54FCT273TMG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CY54FCT273TMG4 |
CY54FCT273TMG4 |
CY54FCT273T 应用技术支持与电子电路设计开发资源下载
- CY54FCT273T 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)