CD74HCT573 具有三态输出的高速 CMOS 逻辑八路透明锁存器

The 'HCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state

	CD74HCT573
Technology Family	HC
Rating	Catalog

CD74HCT573 特性

• 4.5-V to 5.5-V VCC Operation
• Wide Operating Temperature Range of –55°C to 125°C
• Balanced Propagation Delays and Transition Times
• Standard Outputs Drive Up to 10 LS-TTL Loads
• Significant Power Reduction Compared to LS-TTL Logic ICs
• Inputs Are TTL-Voltage Compatible

CD74HCT573 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
CD74HCT573E	ACTIVE	-55 to 125	0.60 | 1ku	PDIP (N) | 20	20 | TUBE
CD74HCT573EE4	ACTIVE	-55 to 125	0.60 | 1ku	PDIP (N) | 20	20 | TUBE
CD74HCT573M	ACTIVE	-55 to 125	0.65 | 1ku	SOIC (DW) | 20	25 | TUBE
CD74HCT573M96	ACTIVE	-55 to 125	0.55 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
CD74HCT573M96E4	ACTIVE	-55 to 125	0.55 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
CD74HCT573M96G4	ACTIVE	-55 to 125	0.55 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
CD74HCT573ME4	ACTIVE	-55 to 125	0.65 | 1ku	SOIC (DW) | 20	25 | TUBE
CD74HCT573MG4	ACTIVE	-55 to 125	0.65 | 1ku	SOIC (DW) | 20	25 | TUBE

CD74HCT573 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CD74HCT573E	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	CD74HCT573E	CD74HCT573E
CD74HCT573EE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	CD74HCT573EE4	CD74HCT573EE4
CD74HCT573M	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT573M	CD74HCT573M
CD74HCT573M96	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT573M96	CD74HCT573M96
CD74HCT573M96E4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT573M96E4	CD74HCT573M96E4
CD74HCT573M96G4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT573M96G4	CD74HCT573M96G4
CD74HCT573ME4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT573ME4	CD74HCT573ME4
CD74HCT573MG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT573MG4	CD74HCT573MG4

CD74HCT573 应用技术支持与电子电路设计开发资源下载

1. CD74HCT573 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)