CD74HCT563 具有三态输出的高速 CMOS 逻辑八路反向透明锁存器

The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.

The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.

The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts

	CD74HCT563
Technology Family	HC
Rating	Catalog

CD74HCT563 特性

• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25°C (Data to Output)
• Fanout (Over Temperature Range)
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il ≤ 1uA at VOL, VOH

CD74HCT563 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
CD74HCT563E	ACTIVE	-55 to 125	0.60 | 1ku	PDIP (N) | 20	20 | TUBE
CD74HCT563EE4	ACTIVE	-55 to 125	0.60 | 1ku	PDIP (N) | 20	20 | TUBE
CD74HCT563M	ACTIVE	-55 to 125	0.65 | 1ku	SOIC (DW) | 20	25 | TUBE
CD74HCT563M96	ACTIVE	-55 to 125	0.55 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
CD74HCT563M96E4	ACTIVE	-55 to 125	0.55 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
CD74HCT563M96G4	ACTIVE	-55 to 125	0.55 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
CD74HCT563ME4	ACTIVE	-55 to 125	0.65 | 1ku	SOIC (DW) | 20	25 | TUBE
CD74HCT563MG4	ACTIVE	-55 to 125	0.65 | 1ku	SOIC (DW) | 20	25 | TUBE

CD74HCT563 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CD74HCT563E	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	CD74HCT563E	CD74HCT563E
CD74HCT563EE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	CD74HCT563EE4	CD74HCT563EE4
CD74HCT563M	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT563M	CD74HCT563M
CD74HCT563M96	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT563M96	CD74HCT563M96
CD74HCT563M96E4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT563M96E4	CD74HCT563M96E4
CD74HCT563M96G4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT563M96G4	CD74HCT563M96G4
CD74HCT563ME4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT563ME4	CD74HCT563ME4
CD74HCT563MG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CD74HCT563MG4	CD74HCT563MG4

CD74HCT563 应用技术支持与电子电路设计开发资源下载

1. CD74HCT563 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)