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CD74HCT259 高速 CMOS 逻辑 8 位可寻址锁存器

The ’HCT259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky.

This latches three active modes and one reset mode. When both the Latch Enable (LE\) and Master Reset (MR\) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR\ and LE\ are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE\ transition from low to high. A condition of LE\ low and MR\ high (Addressable Latch mode) allows the addressed latch’s output to follow the data input; all other latches are unaffected

CD74HCT259
Rating Military
Technology Family HCT
CD74HCT259 特性
CD74HCT259 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
CD74HCT259E ACTIVE -55 to 125 0.46 | 1ku PDIP (N) | 16 25 | TUBE CD74HCT259E
CD74HCT259EE4 ACTIVE -55 to 125 0.46 | 1ku PDIP (N) | 16 25 | TUBE CD74HCT259E
CD74HCT259M ACTIVE -55 to 125 0.50 | 1ku SOIC (D) | 16 40 | TUBE HCT259M
CD74HCT259M96 ACTIVE -55 to 125 0.42 | 1ku SOIC (D) | 16 2500 | LARGE T&R HCT259M
CD74HCT259M96E4 ACTIVE -55 to 125 0.42 | 1ku SOIC (D) | 16 2500 | LARGE T&R HCT259M
CD74HCT259M96G4 ACTIVE -55 to 125 0.42 | 1ku SOIC (D) | 16 2500 | LARGE T&R HCT259M
CD74HCT259ME4 ACTIVE -55 to 125 0.50 | 1ku SOIC (D) | 16 40 | TUBE HCT259M
CD74HCT259MG4 ACTIVE -55 to 125 0.50 | 1ku SOIC (D) | 16 40 | TUBE HCT259M
CD74HCT259MT ACTIVE -55 to 125 0.75 | 1ku SOIC (D) | 16 250 | SMALL T&R HCT259M
CD74HCT259MTE4 ACTIVE -55 to 125 0.75 | 1ku SOIC (D) | 16 250 | SMALL T&R HCT259M
CD74HCT259MTG4 ACTIVE -55 to 125 0.75 | 1ku SOIC (D) | 16 250 | SMALL T&R HCT259M
CD74HCT259 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
CD74HCT259E Pb-Free (RoHS) CU NIPDAU N/A for Pkg Type CD74HCT259E CD74HCT259E
CD74HCT259EE4 Pb-Free (RoHS) CU NIPDAU N/A for Pkg Type CD74HCT259EE4 CD74HCT259EE4
CD74HCT259M Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259M CD74HCT259M
CD74HCT259M96 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259M96 CD74HCT259M96
CD74HCT259M96E4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259M96E4 CD74HCT259M96E4
CD74HCT259M96G4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259M96G4 CD74HCT259M96G4
CD74HCT259ME4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259ME4 CD74HCT259ME4
CD74HCT259MG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259MG4 CD74HCT259MG4
CD74HCT259MT Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259MT CD74HCT259MT
CD74HCT259MTE4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259MTE4 CD74HCT259MTE4
CD74HCT259MTG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT259MTG4 CD74HCT259MTG4
CD74HCT259 应用技术支持与电子电路设计开发资源下载
  1. CD74HCT259 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)