CD74HCT165 高速 CMOS 逻辑 8 位串行输入/并行输出移位寄存器
The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (Q7 and Q\7) available from the last stage. When the parallel load (PL\) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When the PL\ is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allow parallel-to-serial converter expansion by typing the Q7 output to the DS input of the succeeding device.
For predictable operation the LOW-to-HIGH transition of CE\ should only take place while CP is HIGH. Also, CP and CE\ should be LOW before the LOW-to-HIGH transition of PL to prevent shifting the data when PL\ goes HIGH
CD74HCT165 特性
- Buffered Inputs
- Asynchronous Parallel Load
- Complementary Outputs
- Fanout (Over Temperature Range)
- Standard Outputs. . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il
1uA at VOL, VOH
CD74HCT165 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD74HCT165E |
ACTIVE |
-55 to 125 |
0.39 | 1ku |
PDIP (N) | 14 |
25 | TUBE |
CD74HCT165E |
| CD74HCT165EE4 |
ACTIVE |
-55 to 125 |
0.39 | 1ku |
PDIP (N) | 14 |
25 | TUBE |
CD74HCT165E |
| CD74HCT165M |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (D) | 14 |
50 | TUBE |
HCT165M |
| CD74HCT165M96 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
SOIC (D) | 14 |
2500 | LARGE T&R |
HCT165M |
| CD74HCT165M96E4 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
SOIC (D) | 14 |
2500 | LARGE T&R |
HCT165M |
| CD74HCT165M96G4 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
SOIC (D) | 14 |
2500 | LARGE T&R |
HCT165M |
| CD74HCT165ME4 |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (D) | 14 |
50 | TUBE |
HCT165M |
| CD74HCT165MG4 |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (D) | 14 |
50 | TUBE |
HCT165M |
CD74HCT165 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD74HCT165E |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HCT165E |
CD74HCT165E |
| CD74HCT165EE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HCT165EE4 |
CD74HCT165EE4 |
| CD74HCT165M |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT165M |
CD74HCT165M |
| CD74HCT165M96 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT165M96 |
CD74HCT165M96 |
| CD74HCT165M96E4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT165M96E4 |
CD74HCT165M96E4 |
| CD74HCT165M96G4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT165M96G4 |
CD74HCT165M96G4 |
| CD74HCT165ME4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT165ME4 |
CD74HCT165ME4 |
| CD74HCT165MG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT165MG4 |
CD74HCT165MG4 |
CD74HCT165 应用技术支持与电子电路设计开发资源下载
- CD74HCT165 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)