CD74HC259 高速 CMOS 逻辑 8 位可寻址锁存器
The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky.
This latches three active modes and one reset mode. When both the Latch Enable (LE\) and Master Reset (MR\) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR\ and LE\ are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE\ transition from low to high. A condition of LE\ low and MR\ high (Addressable Latch mode) allows the addressed latch’s output to follow the data input; all other latches are unaffected
|
CD74HC259 |
| Rating |
Military |
| Technology Family |
HC |
CD74HC259 特性
- Buffered Inputs and Outputs
- Four Operating Modes
- Typical Propagation Delay of 15ns at VCC = 5V, CL = 15pF, TA = 25°C
- Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
- Wide Operating Temperature Range... –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 
1uA at VOL, VOH
CD74HC259 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD74HC259E |
ACTIVE |
-55 to 125 |
0.46 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
CD74HC259E |
| CD74HC259EE4 |
ACTIVE |
-55 to 125 |
0.46 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
CD74HC259E |
| CD74HC259M |
ACTIVE |
-55 to 125 |
0.50 | 1ku |
SOIC (D) | 16 |
40 | TUBE |
HC259M |
| CD74HC259M96 |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (D) | 16 |
2500 | LARGE T&R |
HC259M |
| CD74HC259M96E4 |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (D) | 16 |
2500 | LARGE T&R |
HC259M |
| CD74HC259M96G4 |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (D) | 16 |
2500 | LARGE T&R |
HC259M |
| CD74HC259ME4 |
ACTIVE |
-55 to 125 |
0.50 | 1ku |
SOIC (D) | 16 |
40 | TUBE |
HC259M |
| CD74HC259MG4 |
ACTIVE |
-55 to 125 |
0.50 | 1ku |
SOIC (D) | 16 |
40 | TUBE |
HC259M |
| CD74HC259MT |
ACTIVE |
-55 to 125 |
0.75 | 1ku |
SOIC (D) | 16 |
250 | SMALL T&R |
HC259M |
| CD74HC259MTE4 |
ACTIVE |
-55 to 125 |
0.75 | 1ku |
SOIC (D) | 16 |
250 | SMALL T&R |
HC259M |
| CD74HC259MTG4 |
ACTIVE |
-55 to 125 |
0.75 | 1ku |
SOIC (D) | 16 |
250 | SMALL T&R |
HC259M |
CD74HC259 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD74HC259E |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HC259E |
CD74HC259E |
| CD74HC259EE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HC259EE4 |
CD74HC259EE4 |
| CD74HC259M |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259M |
CD74HC259M |
| CD74HC259M96 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259M96 |
CD74HC259M96 |
| CD74HC259M96E4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259M96E4 |
CD74HC259M96E4 |
| CD74HC259M96G4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259M96G4 |
CD74HC259M96G4 |
| CD74HC259ME4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259ME4 |
CD74HC259ME4 |
| CD74HC259MG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259MG4 |
CD74HC259MG4 |
| CD74HC259MT |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259MT |
CD74HC259MT |
| CD74HC259MTE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259MTE4 |
CD74HC259MTE4 |
| CD74HC259MTG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC259MTG4 |
CD74HC259MTG4 |
CD74HC259 应用技术支持与电子电路设计开发资源下载
- CD74HC259 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)