CD74HC138-Q1 汽车类高速 CMOS 逻辑 3 至 8 线路解码器多路解复用器（反向和非反向）
The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.
Two active-low and one active-high enables (E1, E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads
CD74HC138-Q1 特性
- Qualified for Automotive Applications
- Select One of Eight Data Outputs Active Low
- I/O Port or Memory Selector
- Three Enable Inputs to Simplify Cascading
- Typical Propagation Delay of 13 ns at VCC = 5 V, CL = 15 pF, TA = 25°C
- Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- 2-V to 6-V VCC Operation
- High Noise Immunity; NIL or NIH = 30% of VCC, VCC = 5 V
CD74HC138-Q1 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD74HC138QM96G4Q1 |
ACTIVE |
-40 to 125 |
0.41 | 1ku |
SOIC (D) | 16 |
2500 |
|
| CD74HC138QM96Q1 |
ACTIVE |
-40 to 125 |
0.41 | 1ku |
SOIC (D) | 16 |
2500 |
|
CD74HC138-Q1 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD74HC138QM96G4Q1 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC138QM96G4Q1 |
CD74HC138QM96G4Q1 |
| CD74HC138QM96Q1 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC138QM96Q1 |
CD74HC138QM96Q1 |
CD74HC138-Q1 应用技术支持与电子电路设计开发资源下载
- CD74HC138-Q1 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)