CD74AC112 具有设置和复位功能的双路下降沿 J-K 触发器
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
| CD74AC112 | |
| Technology Family | AC |
| Rating | Military |
CD74AC112 特性
- AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
- Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
- Balanced Propagation Delays
- ±24-mA Output Drive Current
- Fanout to 15 F Devices
- SCR-Latchup-Resistant CMOS Process and Circuit Design
- Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
CD74AC112 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| CD74AC112E | ACTIVE | -55 to 125 | 0.34 | 1ku | PDIP (N) | 16 | 25 | TUBE | CD74AC112E |
| CD74AC112EE4 | ACTIVE | -55 to 125 | 0.34 | 1ku | PDIP (N) | 16 | 25 | TUBE | CD74AC112E |
| CD74AC112M96 | ACTIVE | -55 to 125 | 0.31 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | AC112M |
| CD74AC112M96E4 | ACTIVE | -55 to 125 | 0.31 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | AC112M |
| CD74AC112M96G4 | ACTIVE | -55 to 125 | 0.31 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | AC112M |
CD74AC112 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| CD74AC112E | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD74AC112E | CD74AC112E |
| CD74AC112EE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD74AC112EE4 | CD74AC112EE4 |
| CD74AC112M96 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD74AC112M96 | CD74AC112M96 |
| CD74AC112M96E4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD74AC112M96E4 | CD74AC112M96E4 |
| CD74AC112M96G4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD74AC112M96G4 | CD74AC112M96G4 |
CD74AC112 应用技术支持与电子电路设计开发资源下载
- CD74AC112 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)