CD54ACT373 具有三态输出的八路透明锁存器

The RCA-CD54/74AC373 and CD54/74AC533 and the CD54/74ACT373 and CD54/74ACT533 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\) is HIGH. When the Latch Enable (LE\) goes LOW, the data is latched. The Output Enable (OE\) controls the 3-sate outputs. When the Output Enable (OE\) is HIGH, the outputs are in the high-impedance state. The latch operation is independent of the state of the Output Enable.

The CD74AC/ACT373 and CD74AC/ACT533 are supplied in 20-lead dual-in-line plastic package (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commerical (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

	CD54ACT373
Technology Family	AC
Rating	Military

CD54ACT373 特性

• Buffered inputs
• Typical pro-agation delay: 4.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
• Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
• SCR-Latchup-resistant CMOS process and circuit design
• Speed of bipolar FAST*/AS/S with significantly reduced power consumption
• Balanced propagation delays
• AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
• ± 24-mA output drive current
  -Fanout to 15 FAST* ICs
  -Drives 50-ohm transmission lines
• Characterized for operation from –40° to 85°C

CD54ACT373 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
CD54ACT373F3A	ACTIVE	-55 to 125	7.45 | 1ku	CDIP (J) | 20	1 | TUBE

CD54ACT373 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CD54ACT373F3A	TBD	A42	N/A for Pkg Type	CD54ACT373F3A	CD54ACT373F3A

CD54ACT373 应用技术支持与电子电路设计开发资源下载

1. CD54ACT373 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)