CD4052B-MIL 具有逻辑电平转换功能的 CMOS 单路 8 通道模拟多路复用器/多路解复用器
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD–VSS = 3V, a VDD–VEE of up to 13V can be controlled; for VDD–VEE level differences above 13V, a VDD–VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE = –13.5V, analog signals from –13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD–VSS and VDD–VEE supply-voltage ranges, independent of the logic state of the control signals.
|
CD4052B-MIL |
| Number of Channels |
8 |
| Pd(Typ)(mW) |
- |
| Configuration |
1 X 1:8 MUX |
| ron(max)(ohms) |
240 |
| tpd max(ns) |
20 |
| Technology Family |
CD4000 |
| Dual Supply (+/-V)(Min)(V) |
2.5 |
| Dual Supply (+/-V)(Max)(V) |
9 |
| Voltage Nodes(V) |
5, 10, 15 |
| IL OFF(Max)(nA) |
+/-1000 |
| RON Mis-match(Max)(Ohms) |
5 |
| ON Time(Max)(ns) |
240 |
| OFF Time(Max)(ns) |
160 |
| Rating |
Military |
| VCC(Min)(V) |
5 |
| VCC(Max)(V) |
18 |
| Pin/Package |
16CDIP |
| Operating Temperature Range(°C) |
-55 to 125 |
CD4052B-MIL 特性
- Wide Range of Digital and Analog Signal Levels
- Digital...3V to 20V
- Analog...
20VP-P
- Low ON Resistance, 125
(Typ) Over 15VP-P Signal Input Range for VDD–VEE = 18V
- High OFF Resistance, Channel Leakage of ±100pA (Typ) at VDD–VEE = 18V
- Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD–VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD–VEE = 20V)
- Matched Switch Characteristics, rON = 5 (Typ) for VDD–VEE = 15V
- Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2uW (Typ) at VDD–VSS = VDD–VEE = 10V
- Binary Address Decoding on Chip
- 5V, 10V and 15V Parametric Ratings
- 10% Tested for Quiescent Current at 20V
- Maximum Input Current of 1uA at 18V Over Full Package Temperature Range, 100nA at 18V and 25°C
- Break-Before-Make Switching Eliminates Channel Overlap
- Applications
- Analog and Digital Multiplexing and Demultiplexing
- A/D and D/A Conversion
- Signal Gating
CD4052B-MIL 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD4052BF |
ACTIVE |
-55 to 125 |
3.13 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
| CD4052BF3A |
ACTIVE |
-55 to 125 |
3.68 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
CD4052B-MIL 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD4052BF |
TBD |
A42 |
N/A for Pkg Type |
CD4052BF |
CD4052BF |
| CD4052BF3A |
TBD |
A42 |
N/A for Pkg Type |
CD4052BF3A |
CD4052BF3A |
CD4052B-MIL 应用技术支持与电子电路设计开发资源下载
- CD4052B-MIL 数据资料 dataSheet 下载.PDF
- TI 德州仪器信号开关产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- 防止模拟开关的额外功耗 (PDF 392 KB) (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)