CD4042B-MIL CMOS 四路时钟“D”锁存器

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.

Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs

	CD4042B-MIL
Voltage Nodes(V)	5, 10, 15
Rating	Military
Technology Family	CD4000

CD4042B-MIL 特性

• Clock polarity control
• Q and Q\ outputs
• Common Clock
• Low power TTL compatible
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (full package-temperature range) =
  1 V at VDD = 5 V
  2 V at VDD = 10 V
  2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Applications:
  • Buffer storage
  • Holding register
  • General digital logic

CD4042B-MIL 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
CD4042BF	ACTIVE	-55 to 125	4.11 | 1ku	CDIP (J) | 16	1 | TUBE
CD4042BF3A	ACTIVE	-55 to 125	4.83 | 1ku	CDIP (J) | 16	1 | TUBE

CD4042B-MIL 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CD4042BF	TBD	A42	N/A for Pkg Type	CD4042BF	CD4042BF
CD4042BF3A	TBD	A42	N/A for Pkg Type	CD4042BF3A	CD4042BF3A

CD4042B-MIL 应用技术支持与电子电路设计开发资源下载

1. CD4042B-MIL 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)