CD4021B-MIL CMOS 8 级静态移位寄存器
CD4014B and CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output form stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line.
|
CD4021B-MIL |
| Voltage Nodes(V) |
5, 10, 15 |
| Technology Family |
CD4000 |
| Rating |
Catalog |
CD4021B-MIL 特性
- Medium speed operation…12 MHz (typ.) clock rate at VDD – VSS = 10 V
- Fully static operation
- 8 master-slave flip-flops plus output buffering and control gating
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Parallel input/serial output data queueing
- Parallel to serial data conversion
- General-purpose register
CD4021B-MIL 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD4021BF |
ACTIVE |
-55 to 125 |
4.66 | 1ku |
CDIP (JT) | 16 |
1 | TUBE |
|
| CD4021BF3A |
ACTIVE |
-55 to 125 |
5.46 | 1ku |
CDIP (JT) | 16 |
1 | TUBE |
|
CD4021B-MIL 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD4021BF |
TBD |
A42 |
N/A for Pkg Type |
CD4021BF |
CD4021BF |
| CD4021BF3A |
TBD |
A42 |
N/A for Pkg Type |
CD4021BF3A |
CD4021BF3A |
CD4021B-MIL 应用技术支持与电子电路设计开发资源下载
- CD4021B-MIL 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)