CD40192B CMOS 可预置 BCD 加/减计数器（具有重置功能的双时钟）
CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\ ENABLE\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\ and BORROW\ outputs for multiple-stage counting schemes are provided.
The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\ ENABLE\ control is low
|
CD40192B |
| Voltage Nodes(V) |
5, 10, 15 |
| Rating |
Catalog |
| Technology Family |
CD4000 |
CD40192B 特性
- Individual clock lines for counting up or counting down
- Synchronous high-speed carry and borrow propagation delays for cascading
- Asynchronous reset and preset capability
- Medium-speed operation–fCL = 8MHz (typ.) @ 10 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Up/down difference counting
- Multistage ripple counting
- Synchronous frequency dividers
- A/D and D/A conversion
- Programmable binary or BCD counting
CD40192B 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD40192BE |
ACTIVE |
-55 to 125 |
1.20 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
| CD40192BEE4 |
ACTIVE |
-55 to 125 |
1.20 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
| CD40192BNSR |
ACTIVE |
-55 to 125 |
1.15 | 1ku |
SO (NS) | 16 |
2000 | LARGE T&R |
|
| CD40192BNSRE4 |
ACTIVE |
-55 to 125 |
1.15 | 1ku |
SO (NS) | 16 |
2000 | LARGE T&R |
|
| CD40192BNSRG4 |
ACTIVE |
-55 to 125 |
1.15 | 1ku |
SO (NS) | 16 |
2000 | LARGE T&R |
|
CD40192B 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD40192BE |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD40192BE |
CD40192BE |
| CD40192BEE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD40192BEE4 |
CD40192BEE4 |
| CD40192BNSR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD40192BNSR |
CD40192BNSR |
| CD40192BNSRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD40192BNSRE4 |
CD40192BNSRE4 |
| CD40192BNSRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD40192BNSRG4 |
CD40192BNSRG4 |
CD40192B 应用技术支持与电子电路设计开发资源下载
- CD40192B 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)