CD4011A CMOS 四路 2 输入与非门
The TI-CD4011A, CD4012A, and CD4023A NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates
These types are supplied in 14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), 14-lead ceramic flat packages (K suffix), and in chip form (H suffix).
| CD4011A | |
| Voltage Nodes(V) | 5, 10, 15 |
| Rating | Catalog |
| Technology Family | CD4000 |
CD4011A 特性
- Quiescent current specified to 15V
- Maximum input leakage of 1 uA at 15 V (full package-temperature range)
- 1-V noise margin (full package-temperature range)
CD4011A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| CD4011AD3 | ACTIVE | -55 to 125 | 13.23 | 1ku | CDIP (J) | 14 | 1 | TUBE |
CD4011A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| CD4011AD3 | TBD | POST-PLATE | N/A for Pkg Type | CD4011AD3 | CD4011AD3 |
CD4011A 应用技术支持与电子电路设计开发资源下载
- CD4011A 数据资料 dataSheet 下载.PDF
- TI 德州仪器门电路产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)