74ACT11074 具有清零和预设功能的双路上升沿 D 类触发器
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (
) or clear (
) input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The 74ACT11074 is characterized for operation from -40°C to 85°C
| 74ACT11074 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | CMOS |
| Output Drive(mA) | -24/24 |
| Output | 3S |
| No. of Bits | 2 |
| Static Current | 0.04 |
| th(ns) | 0 |
| tpd max(ns) | 9.4 |
| tsu(ns) | 4.5 |
| Technology Family | ACT |
| Rating | Catalog |
74ACT11074 特性
- Inputs Are TTL-Voltage Compatible
- Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)
74ACT11074 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ACT11074D | ACTIVE | -40 to 85 | 1.60 | 1ku | SOIC(D) | 14 | 50 | TUBE | |
| 74ACT11074DE4 | ACTIVE | -40 to 85 | 1.60 | 1ku | SOIC(D) | 14 | 50 | TUBE | |
| 74ACT11074DG4 | ACTIVE | -40 to 85 | 1.60 | 1ku | SOIC(D) | 14 | 50 | TUBE | |
| 74ACT11074DR | ACTIVE | -40 to 85 | 1.35 | 1ku | SOIC(D) | 14 | 2500 | LARGE T&R | |
| 74ACT11074DRE4 | ACTIVE | -40 to 85 | 1.35 | 1ku | SOIC(D) | 14 | 2500 | LARGE T&R | |
| 74ACT11074DRG4 | ACTIVE | -40 to 85 | 1.35 | 1ku | SOIC(D) | 14 | 2500 | LARGE T&R | |
| 74ACT11074N | ACTIVE | -40 to 85 | 1.45 | 1ku | PDIP(N) | 14 | 25 | TUBE | |
| 74ACT11074NE4 | ACTIVE | -40 to 85 | 1.45 | 1ku | PDIP(N) | 14 | 25 | TUBE | |
| 74ACT11074PWLE | OBSOLETE | -40 to 85 | TSSOP(PW) | 14 | |||
| 74ACT11074PWR | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP(PW) | 14 | 2000 | LARGE T&R | |
| 74ACT11074PWRE4 | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP(PW) | 14 | 2000 | LARGE T&R | |
| 74ACT11074PWRG4 | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP(PW) | 14 | 2000 | LARGE T&R |
74ACT11074 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ACT11074D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074D | 74ACT11074D |
| 74ACT11074DE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074DE4 | 74ACT11074DE4 |
| 74ACT11074DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074DG4 | 74ACT11074DG4 |
| 74ACT11074DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074DR | 74ACT11074DR |
| 74ACT11074DRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074DRE4 | 74ACT11074DRE4 |
| 74ACT11074DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074DRG4 | 74ACT11074DRG4 |
| 74ACT11074N | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | 74ACT11074N | 74ACT11074N |
| 74ACT11074NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | 74ACT11074NE4 | 74ACT11074NE4 |
| 74ACT11074PWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074PWR | 74ACT11074PWR |
| 74ACT11074PWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074PWRE4 | 74ACT11074PWRE4 |
| 74ACT11074PWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ACT11074PWRG4 | 74ACT11074PWRG4 |
74ACT11074 应用技术支持与电子电路设计开发资源下载
- 74ACT11074 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)