汽车级 STM8AF6146 8位MCU,32KB Flash,EEPROM,10位ADC,定时器,及SPI,I2C接口LQFP-32封装
This datasheet refers to the STM8AF61xx and STM8AH61xx products with 16 to 32 Kbytes of program memory. The STM8AF61xx and STM8AH61xx are hereafter referred to as the STM8AF/H61xx. ‘F’ refers to product versions with data EEPROM and ‘H’ refers to product versions without EEPROM. The identifiers ‘F’ and ‘H’ do not both appear in an order code.
The datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information.
- For complete information on the STM8A microcontroller memory, registers and peripherals, please refer to STM8A microcontroller family reference manual (RM0009).
- For information on programming, erasing and protection of the internal Flash memory please refer to the STM8 Flash programming manual (PM0047).
- For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).
- For information on the STM8 core, please refer to the STM8 CPU programming manual(PM0044).
| Part numbers: STM8AF61xx/STM8AH61xx |
| STM8AF6168, STM8AF6148 STM8AF6166, STM8AF6146 |
STM8AF6146 订购型号:
| Ordering Model | Marketing Status | Package | Core | FLASH Size | Internal RAM Size | A/D Converter | 12 or 16-bit timer (IC/OC/PWM) | 8-bit timer (IC/OC/PWM) | Other timer functions | Serial Interface | Supply Voltage(Vcc) | Supply Voltage(Vcc) | Other Functions |
| nom | nom | min | max | ||||||||||
| kB | B | V | V | ||||||||||
| STM8AF6146TAY | Proposal | LQFP 32 7x7x1.4 1 | STM8 | 16 | 2048 | 7x10-bit | 2(6/6/6) | 1(0/0/0) | WDG, WWDG,AWU | LIN(UART),SPI | 3 | 5.5 | Single-Wire Debug, Independent WDG Clock, 2 Internal RC Oscillators |
| STM8AF6146TCY | Proposal | LQFP 32 7x7x1.4 1 | STM8 | 16 | 2048 | 7x10-bit | 2(6/6/6) | 1(0/0/0) | WDG, WWDG,AWU | LIN(UART),SPI | 3 | 5.5 | Single-Wire Debug, Independent WDG Clock, 2 Internal RC Oscillators |
STM8AF6146 产品特点
- Core
— Max fCPU: 16 MHz
— Advanced STM8A core with Harvard architecture and 3-stage pipeline
— Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark - Memories
— Program memory: 16 to 32 Kbytes Flash; data retention 20 years at 55 °C after 1 kcycle
— Data memory: 0.5 to 1 Kbyte true data EEPROM; endurance 300 kcycles
— RAM: 1 to 2 Kbytes - Clock management
— Low power crystal resonator oscillator with external clock input
— Internal, user-trimmable 16 MHz RC and low power 128 kHz RC oscillators
— Clock security system with clock monitor - Reset and supply management
— Multiple low power modes (wait, slow, auto wake-up, halt) with user inable clock gating
— Low consumption power-on and power-down reset - Interrupt management
— Nested interrupt controller with 32 interrup vectors
— Up to 35 external interrupts on 5 vectors - Timers
— Up to 2 auto-reload 16-bit PWM timers with up to 3 CAPCOM channels each (IC, OC or PWM)
— Multipurpose timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
— 8-bit AR system timer with 8-bit prescaler
— Auto wake-up timer
— 2 watchdog timers: Window and standard - Communication interfaces
— LINUART LIN 2.1 compliant, master/slave modes with automatic resynchronization
— SPI interface up to 8 Mbit/s or (fCPU/2)
— I2C interface up to 400 Kbit/s - Analog to digital converter (ADC)
— 10-bit, 3 LSB ADC with up to 10 multiplexed channels with individual data buffer
— Analog watchdog, scan and continuous sampling mode - I/Os
— Up to 38 user pins including 10 high sink I/Os
— Highly robust I/O design, immune against current injection
STM8AF6146 技术支持与电子电路设计开发资源下载
- ST 意法8位汽车微控制器STM8AF6146 数据手册 DataSheet 下载.pdf
- STM8微控制器选型指南
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