| VIN (min) (V) | 3 |
| VIN (max) (V) | 12 |
| VOUT (min) (V) | 0.8 |
| VOUT (max) (V) | 1.55 |
| IOUT (max) (A) | >60 |
The ISL6569A provides core-voltage regulation by driving two interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output ripple currents. The reduction in ripple results in lower component cost, reduced dissipation, and a smaller implementation area.
The ISL6569A uses cost and space-saving rDS(ON) sensing for channel current balance, active voltage positioning, and over-current protection. Output voltage is monitored by an internal differential remote sense amplifier. A high-bandwidth error amplifier drives the output voltage to match the programmed 5-bit DAC reference voltage. The resulting compensation signal guides the creation of pulse width modulated (PWM) signals to control companion Intersil MOSFET drivers. The OFS pin allows direct offset of the DAC voltage from 0V to 50mV using a single external resistor. The reference and amplifiers are trimmed to ensure a system accuracy of ±0.5% over temperature.
Outstanding features of this controller IC include Dynamic VIDTM technology allowing seamless on-the-fly VID changing without the need of any external components. Output voltage "droop" or active voltage positioning is optional. When employed, it allows the reduction in size and cost of the output capacitors required to support load transients. A threshold-sensitive enable input allows the use of an external resistor divider for start-up coordination with Intersil MOSFET drivers or any other devices powered from a separate supply.
Superior over-voltage protection is achieved by gating on the lower MOSFET of all phases to crowbar the output voltage. An optional second crowbar on VIN, formed with an external MOSFET or SCR gated by the OVP pin, is triggered when an over-voltage condition is detected. Under-voltage conditions are detected, but PWM operation is not disrupted. Over-current conditions cause a hiccup-mode response as the controller repeatedly tries to restart. After a set number of failed startup attempts, the controller latches off. A power good logic signal indicates when the converter output is between the UV and OV thresholds.
| 芯片型号 | 产品状态 | 温度范围 | 封装尺寸图 | 潮湿敏感度等级MSL | 美元价格US $ |
| ISL6569ACBZ | 量产 | 民用级 | 24 Ld SOIC | 3 | 1.84 |
| ISL6569ACBZ-T | 量产 | 民用级 | 24 Ld SOIC T+R | 3 | 1.84 |
| ISL6569ACRZ | 量产 | 民用级 | 32 Ld QFN | 3 | 1.89 |
| ISL6569ACRZ-T | 量产 | 民用级 | 32 Ld QFN T+R | 3 | 1.89 |
| ISL6569ACB | 停产 | 民用级 | 24 Ld SOIC | 1 | N/A |
| ISL6569ACB-T | 停产 | 民用级 | 24 Ld SOIC T+R | 1 | N/A |
| ISL6569ACR | 停产 | 民用级 | 32 Ld QFN | 1 | N/A |
| ISL6569ACR-T | To Be Discontinued | 民用级 | 32 Ld QFN T+R | 1 | 1.89 |