VIN (min) (V) | 3 |
VIN (max) (V) | 12 |
VOUT (min) (V) | 0.8375 |
VOUT (max) (V) | 1.65 |
IOUT (max) (A) | >120 |
The ISL6565A, ISL6565B controls microprocessor core voltage regulation by driving up to 3 synchronous-rectified buck channels in parallel. Multiphase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents.
The difference between the ISL6565A and the ISL6565B is that the ISL6565A utilizes rDS(ON) current sensing, while the ISL6565B utilizes DCR current sensing for each phase. These cost and space saving methods of current sensing are used for adaptive voltage positioning (droop), channelcurrent balancing, and overcurrent protection. To ensure the accuracy of droop, a programmable internal temperature compensation function is implemented to compensate the effect of rDS(ON) and DCR temperature sensitivity.
A unity gain, differential amplifier is provided for remote voltage sensing. Any potential difference between remote and local grounds is eliminated using the remote-sense amplifier. The precision threshold-sensitive enable input is available to accurately coordinate the start up of the ISL6565A, ISL6565B with Intersil MOSFET driver ICs. Dynamic-VIDTM technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting.
芯片型号 | 产品状态 | 温度范围 | 封装尺寸图 | 潮湿敏感度等级MSL | 美元价格US $ |
ISL6565BCBZ | 量产 | 民用级 | 28 Ld SOIC | 3 | 2.02 |
ISL6565BCBZ-T | 量产 | 民用级 | 28 Ld SOIC T+R | 3 | 2.02 |
ISL6565BCRZ | 量产 | 民用级 | 32 Ld QFN | 3 | 2.07 |
ISL6565BCRZ-T | 量产 | 民用级 | 32 Ld QFN T+R | 3 | 2.07 |
ISL6565BCVZ | 量产 | 民用级 | 28 Ld TSSOP | 3 | 2.07 |
ISL6565BCVZ-T | 量产 | 民用级 | 28 Ld TSSOP T+R | 3 | 2.07 |
ISL6565BCB | 停产 | 民用级 | 28 Ld SOIC | 1 | N/A |
ISL6565BCB-T | 停产 | 民用级 | 28 Ld SOIC T+R | 1 | N/A |
ISL6565BCR | 停产 | 民用级 | 32 Ld QFN | 1 | N/A |
ISL6565BCR-T | 停产 | 民用级 | 32 Ld QFN T+R | 1 | N/A |
ISL6565BCV | 停产 | 民用级 | 28 Ld TSSOP | 1 | N/A |
ISL6565BCV-T | 停产 | 民用级 | 28 Ld TSSOP T+R | 1 | N/A |