| VIN (min) (V) | 3.3 |
| VIN (max) (V) | 24 |
| VOUT (min) (V) | 0.9 |
| VOUT (max) (V) | 5.5 |
| IOUT (max) (A) | 8 |
The ISL6225 dual PWM controller delivers high efficiency and tight regulation from two voltage regulating synchronous buck DC/DC converters. The ISL6225 PWM power supply controller was designed especially for DDR DRAM, SDRAM, and graphic chipset applications in high performance desknote PCs, notebook PCs, sub-notebook PCs, and PDAs.
Automatic mode selection of constant-frequency synchronous rectification at heavy load, and hysteretic diode-emulation at light load, assure high efficiency over a wide range of conditions. The hysteretic mode of operation can be disabled separately on each PWM converter if constant-frequency continuous-conduction operation is desired for all load levels. Efficiency is further enhanced by using the lower MOSFET rDS(ON) as the current sense element.
Voltage-feed-forward ramp modulation, average current mode control, and internal feedback compensation provide fast response to input voltage and output load transients. Input current ripple is minimized by channel to channel PWM phase shift of 0°, 90°, or 180° determined by input voltage and status of the DDR pin.
The ISL6225 can control two independent output voltages adjustable from 0.9V to 5.5V or, by activating the DDR pin, transform into a complete DDR memory power supply solution. In DDR mode, CH2 output voltage VTT tracks CH1 output voltage VDDQ. CH2 output can both source and sink current, an essential power supply feature for DDR memory systems. The reference voltage VREF required by DDR memory is generated as well.
In dual power supply applications the ISL6225 monitors the output voltage of both CH1 and CH2. An independent PGOOD (power good) signal is asserted for each channel after the soft-start sequence has completed, and the output voltage is within ±10% of the set point. In DDR mode CH1 generates the only PGOOD signal.
Built-in overvoltage protection prevents the output from going above 115% of the set point by holding the lower MOSFET on and the upper MOSFET off. When the output voltage decays below the overvoltage threshold, normal operation automatically resumes. Once the soft-start sequence has completed, under-voltage protection may latch the ISL6225 off if either output drops below 75% of its set point value.
Adjustable overcurrent protection (OCP) monitors the voltage drop across the rDS(ON) of the lower MOSFET. If more precise current-sensing is required, an external current sense resistor may be used.
| 芯片型号 | 产品状态 | 温度范围 | 封装尺寸图 | 潮湿敏感度等级MSL | 美元价格US $ |
| ISL6225CAZ | 量产 | 民用级 | 28 Ld QSOP | 3 | 2.47 |
| ISL6225CAZ-T | 量产 | 民用级 | 28 Ld QSOP T+R | 3 | 2.52 |
| ISL6225CAZA | 量产 | 民用级 | 28 Ld QSOP | 3 | 2.47 |
| ISL6225CAZA-T | 量产 | 民用级 | 28 Ld QSOP T+R | 3 | 2.52 |
| ISL6225CA | 停产 | 民用级 | 28 Ld QSOP | 1 | N/A |
| ISL6225EVAL1 | 停产 | 民用级 | 评估板 | N/A | N/A |
| ISL6225EVAL2 | 停产 | 民用级 | 评估板 | N/A | N/A |
| ISL6225CA-T | To Be Discontinued | 民用级 | 28 Ld QSOP T+R | 1 | 2.52 |